Power is the number one design challenge for nanometer
designs today. Due to the power integrity issues, engineers are
faced with either over-designed grid with high congestion and
wasted resources or failed silicon and low yield.
Apache's Complete Dynamic Power Integrity solution takes power
integrity to the next level by addressing the growing complexity
of dynamic power issues, such as low power design verification
and IC/package co-verification. From prototyping to sign-off,
Apache's power closure flow enables designers to identify the
dynamic "hot spots", analyze its impact on timing, and
automatically fix the sources of noise.
Silicon proven with more than 100 successful production tapeouts
by major semiconductor companies, Apache's solution enables
designers to analyze and fix power integrity issues prior to
tapeout, while avoiding unnecessary over-designing of the grid.
Technology, Inc. develops and provides leading edge solutions
for the characterization,
validation, and verification
of embedded memory.
Based on the memory
instance's layout netlist with parasitic RC, it can generate
more accurate timing and power model (in Synopsys .lib format)
than the model generated by memory compiler.
It is a full automatic
solution, which can
perform what-if (any temperature, any voltage, any spice model,
any slew-rate and output loading) analysis to meet customer's
needs. It can be adopted to do in-house memory and external
memory IP characterization,
what-if analysis, process verification, etc. Their partial customer
list: TSMC, UMC, Hynix, Charter, Tower, Faraday, Verisilicon,
Virtual Silicon, etc.
focuses on high-end IP solutions for the USB and PCI protocol
standards and their evolutions (SuperSpeed USB, PCI Express,
PCI-X). We offer comprehensive intellectual property (IP)
solutions to a global market; our solution includes
semiconductor design IP (controllers and bridges) for ASIC,
structured ASIC, and FPGA, hardware design platforms, low-level
software, customization services, and dedicated technical
since its inception in 1996, PLDA is privately owned and has
reported increasing profits ever since its creation. Our success
is based on doing one thing very well！Intellectual
Property (IP) Cores and their design environments, for designers
of ASIC, Structured-ASIC, and FPGA.
With over one thousand
designs in production silicon (and counting), PLDA provides the
safest, most complete, and most flexible IP solutions for USB
and PCI implementation.
TOOL is a company that creates the software products. Our
experience and original technology have produced very unique and
competitive package software such as the major product LAVIS.
LAVIS is a versatile layout visualization platform supporting
fast large data display and multiple file formats.
Large data support: LAVIS is able to handle 64bit address/large file, and it is
applicable to large amount of data over 2GB.
Multi-Format support: GDSII ,
OASIS , LEF/DEF , MEBES , JEOL , HL , TOSHIBA(VSB-11,12)
LAVIS has high-speed display system, and the user will not
be stressed when handling large amount of data.
And an efficient memory control system allows the operation
with the minimum memory for large amount of data.